`timescale 1ns/1ns
module add_half (
           input A,
           input B,

           output wire S,
           output wire C
       );

assign S = A ^ B;
assign C = A & B;

endmodule


module add_full(
    input A,
    input B,
    input Ci,

    output wire S,
    output wire Co
);

wire s1;
wire c1;
wire c2;
add_half u_add_half1(
    .A ( A ),
    .B ( B ),
    .S ( s1 ),
    .C  ( c1  )
);

add_half u_add_half2(
    .A ( s1 ),
    .B ( Ci ),
    .S ( S ),
    .C  ( c2  )
);

assign Co=c1|c2;
// add_half u_add_half3(
//     .A ( s2 ),
//     .B ( c1 ),
//     .S ( s3 ),
//     .C  ( c3  )
// );

endmodule
